Circuitized substrates such as printed circuit boards (hereinafter also referred to as PCBs), chip carriers, and the like are typically constructed in laminate form in which several layers of dielectric material and conductive material (laminates) are bonded together using relatively high temperature and pressure lamination processes. The conductive layers, typically of thin copper, are usually used in the formed substrate for providing electrical connections to and among various devices located on the surface of the substrate, examples of such devices being integrated circuits (semiconductor chips) and discrete passive devices, such as capacitors, resistors, inductors, and the like. The discrete passive devices occupy a high percentage of the surface area of the completed substrate, which is undesirable because of the increased demand for miniaturization of products. In order to increase the available substrate surface area, multiple functions can be provided on a single component for mounting on a board. When passive devices are in such a configuration, these are often referred to as integral passive devices, meaning that the functions are integrated into the singular component. Because of such external positioning, however, these components still utilize, albeit less than if in singular form, valuable board real estate. In response, there have also been efforts to embed discrete passive components within the board.
A capacitor designed for disposition within a PCB substrate may thus be referred to as an embedded integral passive component or, more simply, an embedded capacitor. Such a capacitor thus provides internal capacitance. The result of this internal positioning is that it is unnecessary to also position such devices externally on the PCB's outer surface(s).
With respect to a fixed capacitor area, two known approaches are available for increasing the planar capacitance (capacitance/area) of an internal capacitor. In one such approach, higher dielectric constant materials can be used, while in a second, the thickness of the dielectric can be reduced. These constraints are reflected in the following formula for capacitance per area:C/A=Dielectric Constant of Laminate X Dielectric Constant in Vacuum/Dielectric Thickness where: C is the capacitance and A is the area of the capacitor.
As mentioned above, there have been attempts to provide internal capacitance and other internal conductive structures, components or devices within circuitized substrates such as PCBs, some of these including the use of nano-powders. The following are some examples of such attempts, including those using nano-powders and those using alternative measures.
U.S. Pat. No. 6,704,207, entitled “Device and Method for Interstitial Components in a Printed Circuit Board,” issued Mar. 9, 2004, discloses a printed circuit board which includes a first layer having first and second surfaces, with an above-board device (e.g., an ASIC chip) mounted thereon. The PCB includes a second layer having third and fourth surfaces. One of the surfaces can include a recessed portion for securely holding an interstitial component. A “via,” electrically connecting the PCB layers, is also coupled to a lead of the interstitial component. The interstitial components include diodes, transistors, resistors, capacitors, thermocouples, and the like.
U.S. Pat. No. 6,616,794, entitled “Integral Capacitance for Printed Circuit Board Using Dielectric Nanopowders” and issued Sep. 9, 2003, discloses a method for producing integral capacitance components for inclusion within printed circuit boards in which hydro-thermally prepared nano-powders permit the fabrication of dielectric layers that offer increased dielectric constants and are readily penetrated by micro-vias. A slurry or suspension of a hydro-thermally prepared nano-powder and solvent is prepared. A suitable bonding material, such as a polymer, is mixed with the nano-powder slurry to generate a composite mixture which is formed into a dielectric layer. The dielectric layer may be placed upon a conductive layer prior to curing, or conductive layers may be applied upon a cured dielectric layer, either by lamination or metallization processes, such as vapor deposition or sputtering.
U.S. Pat. No. 6,544,651, entitled “High Dielectric Constant Nano-Structure Polymer-Ceramic Composite” and issued Apr. 3, 2003, discloses a polymer-ceramic composite having high dielectric constants formed using polymers containing a metal acetylacetonate (acacs) curing catalyst. In particular, a certain percentage of Co (III) may increase the dielectric constant of a certain epoxy. The high dielectric polymers are combined with fillers, preferably ceramic fillers, to form two-phase composites having high dielectric constants.
U.S. Pat. No. 6,395,996, entitled “Multi-layered Substrate With Built-In Capacitor Design” and issued May 28, 2002, discloses a multi-layered substrate having built-in capacitors which are used to decouple high frequency noise generated by voltage fluctuations between a power plane and a ground plane of a multi-layered substrate. At least one kind of dielectric material, which has filled-in through holes between the power plane and the ground plane and includes a high dielectric constant, is used to form the built-in capacitors.
U.S. Pat. No. 6,068,782, entitled “Individual Embedded Capacitors for Laminated Printed Circuit Boards” and issued May 30, 2000, discloses a method of fabricating individual, embedded capacitors in multi-layer printed circuit boards. The capacitor fabrication is based on a sequential build-up technology employing a first pattern-able insulator. After patterning of the insulator, pattern grooves are filled with a high dielectric constant material, typically a polymer/ceramic composite. Capacitance values are defined by the pattern size, thickness and dielectric constant of the composite. Capacitor electrodes and other electrical circuitry can be created either by etching laminated copper, by metal evaporation, or by depositing conductive ink.
U.S. Pat. No. 5,162,977, entitled “Printed Circuit Board Having an Integrated Decoupling Capacitive Element” and issued Nov. 10, 1992, discloses a PCB which includes a high capacitance power distribution core, the manufacture of which is compatible with standard printed circuit board assembly technology. The high capacitance core consists of a ground plane and a power plane separated by a planar element having a high dielectric constant. The high dielectric constant material is typically glass fiber impregnated with a bonding material, such as epoxy resin loaded with a ferro-electric ceramic substance having a high dielectric constant. The ferro-electric ceramic substance is typically a nano-powder combined with an epoxy bonding material. Pre-fired and ground ceramic nano-powder particles have a typical dimension in the range of 500-20,000 nanometers. Furthermore, the particle distribution in this range is generally rather broad, meaning that there could be a 10,000 nm particle alongside a 500 nm particle.
The distribution within the dielectric layer of particles of different size often presents major obstacles to thru-hole formation where the thru-holes are of extremely small diameter, also referred to in the industry as micro-vias, due to the presence of the larger particles. Another problem associated with pre-fired ceramic nano-powders is the ability for the dielectric layer to withstand substantial voltage without breakdown occurring across the layer. Typically, capacitance layers within a PCB are expected to withstand at least 300 volts in order to qualify as a reliable component for PCB construction. The presence of the comparatively larger ceramic particles in pre-fired ceramic nano-powders within a capacitance layer prevents extremely thin layers from being used because the boundaries of contiguous large particles provide a path for voltage breakdown. This is even further undesirable because, as indicated by the equation cited above, greater planar capacitance may also be achieved by reducing the thickness of the dielectric layer. The thickness is thus limited by the size of the particles therein.
U.S. Pat. No. 5,079,069, entitled “Capacitor Laminate for Use in Capacitive Printed Circuit Boards and Methods of Manufacture” and issued Jan. 7, 1992, discloses a capacitor laminate to provide a bypass capacitive function for devices mounted on the PCB, the capacitor laminate being formed of conventional conductive and dielectric layers whereby each individual external device is provided with capacitance by a proportional portion of the capacitor laminate and by borrowed capacitance from other portions of the capacitor laminate, the capacitive function of the capacitor laminate being dependent upon random firing or operation of the devices. That is, the resulting PCB still requires the utilization of external devices thereon, and thus does not afford the PCB external surface area real estate savings mentioned above.
U.S. Pat. No. 7,078,816 for “Circuitized Substrate”, issued Jul. 18, 2006 to Robert Japp et al teaches a circuitized substrate comprising a first layer comprising a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer.
U.S. Pat. Publication No. 2006/0151863 for “Capacitor Material for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized Substrate”, on application filed Jul. 13, 2006 by Rabindra N. Das et al teaches a material for use as part of an internal capacitor within a circuitized substrate including a polymer (e.g., a cycloaliphatic epoxy or phenoxy based) resin and a quantity of nano-powders of ferroelectric ceramic material (e.g., barium titanate).
U.S. Pat. Publication No. 2006/0154434 for “Method of Making an Internal Capacitive Substrate for Use in a Circuitized Substrate And Method of Making Said Circuitized Substrate”, on application filed Jul. 13, 2006 by Rabindra N. Das et al teaches a method of forming a capacitive substrate in which first and second conductors are formed opposite a dielectric, with one of these electrically coupled to a thru-hole connection. Each functions as an electrode for the resulting capacitor. The substrate is then adapted for being incorporated within a larger structure to form a circuitized substrate such as a printed circuit board or a chip carrier.
U.S. Pat. Publication No. 2006/0154501 for “Capacitor Material With Metal Component for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized Substrate”, on application filed Jul. 13, 2006 discloses a material for use as part of an internal capacitor within a circuitized substrate. A polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ferroelectric ceramic component are provided.
U.S. Pat. Publication No. 2007/0010064 for “Method of Making a Capacitive Substrate Using Photoimageable Dielectric For Use as Part of a Larger Circuitized Substrate, Method of Making Said Circuitized Substrate and Method of Making an Information Handling System Including Said Circuitized Substrate” on application filed by Rabindra N. Das et al teaches a method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. Photoimageable material is used to facilitate positioning of the capacitive dielectric being printed. The capacitive substrate may be incorporated within a larger circuitized substrate to form an electrical assembly.
U.S. Patent Publication No. 2007/0010065 for “Method of Making a Capacitive Substrate For Use as Part of a Larger Circuitized Substrate, Method of Making Said Circuitized Substrate and Method of Making an Information Handling System Including Said Circuitized Substrate”, on application filed Jan. 11, 2007 by Rabindra N. Das et al teaches a method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate.
U.S. Pat. Publication No. 2007/0177331 for “Non-Flaking Capacitor Material, Capacitive Substrate Having an Internal Capacitor Therein Including Said Non-Flaking Capacitor Material, and Method of Making a Capacitor Member for Use in a Capacitive Substrate”, on application filed Aug. 2, 2007 by Rabindra N. Das et al teaches a capacitor material including a thermosetting resin, a high molecular mass flexibilizer, and a quantity of nano-particles of a ferroelectric ceramic material, the capacitor material not including continuous or semi-continuous fibers as part thereof. The material is adapted for being positioned in layer form on a first conductor member and heated to a predetermined temperature whereupon the material will not possess any substantial flaking characteristics. A second conductor member may then be positioned on the material to form a capacitor member, which then may be incorporated within a substrate to form a capacitive substrate. Electrical components may be positioned on the substrate and capacitively coupled to the internal capacitor.
U.S. Pat. Publication No. 2007/0275525 for “Capacitive Substrate and Method of Making Same”, on application filed Nov. 29, 2007 by Rabindra N. Das et al teaches a capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
The teachings of the above patents and co-pending applications listed above are incorporated herein by reference.
With respect to commercially available dielectric powders which have been used in internal conductive structures such as mentioned in some of the above patents, among these being metal titanate-based powders, such powders are known to be produced by a high-temperature, solid-state reaction of a mixture of the appropriate stoichiometric amounts of oxides or oxide precursors (e.g., carbonates, hydroxides or nitrates) of barium, calcium, titanium, and the like. In such calcination processes, the reactants are wet-milled to accomplish a desired final mixture. The resulting slurry is dried and fired at elevated temperatures, sometimes as high as 1,300 degrees C., to attain the desired solid-state reactions. Thereafter, the fired product is milled to produce a powder. Although the pre-fired and ground dielectric formulations produced by solid phase reactions are acceptable for many electrical applications, these suffer from several disadvantages. First, the milling step serves as a source of contaminants, which can adversely affect electrical properties. Second, the milled product consists of irregularly shaped fractured aggregates which are often too large and possess a wide particle size distribution, 500-20,000 nm. Consequently, films produced using these powders are limited to thicknesses greater than the size of the largest particle. Third, powder suspensions or composites produced using pre-fired ground ceramic powders must be used immediately after dispersion, due to the high sedimentation rates associated with large particles. The stable crystalline phase of barium titanate for particles greater than 200 nm is tetragonal and, at elevated temperatures, a large increase in dielectric constant occurs due to a phase transition. It is thus clear that methods of making PCBs which rely on the advantageous features of using nano-powders as part of the PCB's internal components possess various undesirable aspects which are detrimental to providing a PCB with optimal functioning capabilities when it comes to internal capacitance or other electrical operation. This is particularly true when the desired final product attempts to meet today's miniaturization demands, including the utilization of high-density patterns of thru-holes therein.
The present invention represents an approach to forming internal capacitors and resistors in a substrate. In the present invention, at least two capacitors may be formed by initially forming a first capacitive substrate, positioning layers of photoimageable material atop the substrate and thereafter removing portions thereof to expose the capacitive substrate's conductors, then forming a quantity of capacitive material on the two exposed conductors. This process eliminates the need for providing an interim dielectric layer and is also capable of being performed using known technologies. Significantly, the capacitors formed using the teachings herein are capable of having nano and/or micro particles as part thereof. It is believed that such a method, as well as a method of forming a larger circuitized substrate including the capacitive substrate, represent significant advancements in the art.